What a schematic review should catch before layout starts

The schematic review is the last cheap checkpoint. A missed pull-up found here is a two-minute edit. Found after layout it is a re-route; found after fab it is a bodge wire and a respin; found in the field it is a recall. The review’s purpose is to spend an hour now to not spend a month later.

This is the checklist we run schematics against before releasing them to layout. It assumes the design is functionally “done” — the point is to find what “done” missed.

Power: the section that causes the most respins

Rail inventory and budget

• List every rail: voltage, tolerance, estimated and worst-case current, source (which regulator), and every load on it. A spreadsheet, not a mental model.
• Check each regulator against its worst-case load including inrush and transient, not typical. Add margin for the load estimate being wrong — 30% is common at this stage.
• Thermal: (Vin − Vout) × I for every linear regulator. An LDO dropping 3.3 V at 500 mA is dissipating 1.65 W and needs a heatsinking copper plan that layout has to know about now.
• Efficiency and input current: does the upstream supply / connector / fuse actually deliver the sum of input currents at low line?

Sequencing

• Does the SoC/FPGA have a required power-up and power-down order? Most do (core before I/O, or a specific ramp relationship). Violating it can cause latch-up or excess current through internal diodes. Check the datasheet’s sequencing section and confirm the design enforces it — enable-pin daisy chains, a sequencer IC, or a supervisor.
• Power-down order matters too, and is more often missed. A rail collapsing in the wrong order can back-drive an I/O bank.
• What happens on a brown-out — does the sequence restart cleanly, or can it hang half-powered?

Decoupling, as schematic intent

• Every power pin has decoupling specified with values and count per the device datasheet. Bulk capacitance per rail sized for the load step.
• It is fine that placement is layout’s job — but the schematic must show the intent so the reviewer can check nothing is missing and layout knows the target.

Reset, clocks, and strapping

• Every reset: source, polarity, pull resistor, RC or supervisor timing, and which devices it reaches. Open-drain resets wired together need one pull-up, not none and not five.
• Reset supervisor threshold matched to the SoC’s minimum operating voltage, with hysteresis, so a sagging rail does not leave the part running out of spec.
• Watchdog: present, wired to actually reset the system, and not defeatable by the failure it is meant to catch.
• Boot strapping / mode pins: this is a classic post-layout disaster. Every strap pin identified, its required level confirmed against the boot-mode table, and the resistor value chosen so it wins against the pin’s other function (often the same pin is a functional I/O with its own loading). Note which straps need to be changeable for bring-up and give them a header or a 0 Ω option.
• Clocks: every oscillator/crystal has the load caps per the crystal spec and the oscillator’s drive level checked. PLL supplies filtered. Spread-spectrum choice made deliberately (it helps EMC, it can hurt a camera or ADC).

Every net: reference and return path

Signal integrity is decided in the schematic by what you connect to what, before a single trace exists.

• For each interface, name the return-current path. A differential pair referenced to a plane that has a split under it will radiate and fail EMC — and the fix is a stitching-cap or plane change that is far easier to plan now.
• Series termination / source termination resistors placed in the schematic for fast single-ended nets (RGMII, parallel memory, fast GPIO). Value TBD by layout, but the footprint must exist.
• Differential pairs (USB, Ethernet, MIPI, PCIe, LVDS): correct AC coupling where the standard requires it, correct common-mode termination, correct polarity, and pairs that the connector pinout does not force to cross.
• Unused inputs tied off, not floating. Unused outputs left open. Unused op-amp sections wired as followers to a mid-rail, not left open-loop.
• Level shifting wherever two voltage domains meet — confirm direction, speed, and that the translator’s supported data rate exceeds the bus.

Connectors and the outside world

Connectors are where field failures enter.

• Pinout sanity: power and ground pins adjacent enough to carry the current; hot-plug order (ground first, then power, then signal) if the connector is ever mated live.
• ESD/EOS protection on every externally accessible pin: USB, Ethernet (plus the magnetics and Bob Smith termination), buttons, connector I/O. TVS diodes with the right stand-off and clamping voltage, placed at the connector.
• Reverse-polarity and overvoltage protection on the power input, sized for the real worst case (a field tech with a 24 V supply on a 12 V input).
• Miswire survival: what happens if the harness is plugged in shifted by one pin? On rugged products this is worth a deliberate answer.
• Test points on every rail, reset, boot strap, and key signal — see DFT.

Design for test and manufacture

• DFT: bed-of-nails or flying-probe access to rails and critical nets. A JTAG/SWD header (even if depopulated in production). A UART console broken out. A way to hold the board in reset and in each boot mode. Programming access for every programmable device, and the programming order/method noted.
• DFM: no parts on both sides that force two reflow passes unless intended; package choices the assembler can place; no 0201s where 0402 would do; fiducials present; polarity markings that survive assembly.
• First-article bring-up plan implied by the schematic: can you bring rails up one at a time? Is there a “populate R1, leave R2 off” staged power-on option?

BOM and component risk

• Lifecycle: any part NRND or single-source? Flag it now; a second source or a footprint that accepts alternates is a schematic decision.
• Ratings with margin: capacitor voltage derating (ceramics lose capacitance with DC bias — a 6.3 V X5R on a 5 V rail may be at half its rated value), resistor power, inductor saturation current at the real peak, MOSFET SOA.
• Tolerance stack-up on anything that sets a threshold, a timing, or a feedback divider.
• Passives count: every DNP is intentional and labelled; every “we’ll tune this in bring-up” has a real footprint and a starting value.

How to actually run it

• Two reviewers minimum, at least one who did not draw the schematic.
• Page by page, net by net on the critical interfaces, out loud, against the device datasheets open on the table — not a glance-through.
• Every datasheet’s “layout guidelines” and “design checklist” section read, because vendors put the expensive mistakes there.
• Track findings as a list with owners and states. The review is not done when the meeting ends; it is done when the list is closed and re-checked.
• Re-review after the fixes. Fixes introduce errors.

The trade-off

A proper schematic review on a medium-complexity board is the better part of a day for two engineers, plus the fix cycle — call it two to three engineer-days before layout even starts. It feels like a delay when the schematic “looks finished”.

What it does not do: it will not catch problems that only exist in the physical layout — coupling, plane resonance, actual trace impedance, thermal reality, mechanical fit. Those need a layout review and, ultimately, measurement on hardware. The schematic review is necessary and cheap; it is not sufficient, and treating a passed schematic review as “the hard part is over” is its own failure mode.